High performance analog to digital converters typically employ a parallel configuration of analog folding circuits to symmetrically fold input signals prior to quantization by high-speed comparators. Such a circuit uses two comparator ladders, having a total of 2(2.sup.n/2 -1) comparators in the two legs together, where n is the bit resolution of the converter. The comparator ladder in each leg performs an n/2 bit binary encoding of the analog input. Because the number of levels depends exponentially on n, the number of comparators which one must employ rises exponentially with circuit resolution. This can make many engineering applications of such circuits expensive. Moreover, skew time--the time lag between receipt of analog input and delivery of quantized output--increases with increasing number of comparators; and as the number of comparators increases, the power they consume does also, leaving less system power available for signal detection, thus reducing system bandwidth.